A methodology and framework to assist in the architecture design and functional verification of complex electronic systems

  1. Tomasena, Koldo
Zuzendaria:
  1. Igone Velez Isasmendi Zuzendaria
  2. Juan Sevillano Berasategui Zuzendaria

Defentsa unibertsitatea: Universidad de Navarra

Fecha de defensa: 2013(e)ko uztaila-(a)k 12

Epaimahaia:
  1. Andrés García-Alonso Montoya Presidentea
  2. Andoni Irizar Picón Idazkaria
  3. Jon Legarda Macon Kidea
  4. Miguel Soto Rodríguez Kidea
  5. Francisco Javier del Pino Suárez Kidea

Mota: Tesia

Teseo: 116321 DIALNET lock_openDadun editor

Laburpena

An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions