A methodology and framework to assist in the architecture design and functional verification of complex electronic systems

  1. Tomasena, Koldo
unter der Leitung von:
  1. Igone Velez Isasmendi Doktorvater/Doktormutter
  2. Juan Sevillano Berasategui Doktorvater/Doktormutter

Universität der Verteidigung: Universidad de Navarra

Fecha de defensa: 12 von Juli von 2013

Gericht:
  1. Andrés García-Alonso Montoya Präsident/in
  2. Andoni Irizar Picón Sekretär/in
  3. Jon Legarda Macon Vocal
  4. Miguel Soto Rodríguez Vocal
  5. Francisco Javier del Pino Suárez Vocal

Art: Dissertation

Teseo: 116321 DIALNET lock_openDadun editor

Zusammenfassung

An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions