Effect of different design stages on the SEU failure rate of FPGA systems

  1. Villalta, I.
  2. Bidarte, U.
  3. Gomez-Cornejo, J.
  4. Jimenez, J.
  5. Cuadrado, C.
Aktak:
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

ISBN: 9781509045655

Argitalpen urtea: 2016

Orrialdeak: 37-42

Mota: Biltzar ekarpena

DOI: 10.1109/DCIS.2016.7845269 GOOGLE SCHOLAR
Datuen iturria: Scopus