Effect of different design stages on the SEU failure rate of FPGA systems

  1. Villalta, I.
  2. Bidarte, U.
  3. Gomez-Cornejo, J.
  4. Jimenez, J.
  5. Cuadrado, C.
Proceedings:
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

ISBN: 9781509045655

Year of publication: 2016

Pages: 37-42

Type: Conference paper

DOI: 10.1109/DCIS.2016.7845269 GOOGLE SCHOLAR
Data source: Scopus