Josu
Jugo García
Universidad Politécnica de Madrid
Madrid, EspañaPublicacións en colaboración con investigadores/as de Universidad Politécnica de Madrid (2)
2019
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FPGA-based interlock system for the chopper of the Linear IFMIF prototype accelerator injector
Fusion Engineering and Design, Vol. 146, pp. 1708-1711
2015
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RIO EPICS device support application case study on an ion source control system (ISHP)
Fusion Engineering and Design