Publicaciones en colaboración con investigadores/as de Universidad del País Vasco/Euskal Herriko Unibertsitatea (79)

2024

  1. Interrupt Latency Accurate Measurement in Multiprocessing Embedded Systems by Means of a Dedicated Circuit

    Electronics (Switzerland), Vol. 13, Núm. 9

2022

  1. Embedded firewall for on-chip bus transactions

    Computers and Electrical Engineering, Vol. 98

  2. Encryption AXI Transaction Core for Enhanced FPGA Security

    Electronics (Switzerland), Vol. 11, Núm. 20

  3. Specific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systems

    Technologies, Vol. 10, Núm. 3

2021

  1. A fixed-latency architecture to secure GOOSE and sampled value messages in substation systems

    IEEE Access, Vol. 9, pp. 51646-51658

  2. A survey on vulnerabilities and countermeasures in the communications of the smart grid

    Electronics (Switzerland), Vol. 10, Núm. 16

  3. Evaluating latency in multiprocessing embedded systems for the smart grid

    Energies, Vol. 14, Núm. 11

  4. Fast and efficient address search in System-on-a-Programmable-Chip using binary trees

    Computers and Electrical Engineering, Vol. 96

2019

  1. Fast and efficient FPGA prototype system for embedded control algorithms in electric traction

    2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019

  2. Smart Sensor: SoC Architecture for the Industrial Internet of Things

    IEEE Internet of Things Journal, Vol. 6, Núm. 4, pp. 6567-6577

2018

  1. SEU emulation in industrial SoCs combining microprocessor and FPGA

    Reliability Engineering and System Safety, Vol. 170, pp. 53-63

  2. System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS

    Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018

2017

  1. Cyber-Physical Production System Gateway Based on a Programmable SoC Platform

    IEEE Access, Vol. 5, pp. 20408-20417

  2. Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

    Microelectronics Reliability, Vol. 78, pp. 85-92

  3. MACsec layer 2 security in HSR rings in substation automation systems

    Energies, Vol. 10, Núm. 2

  4. On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems

    IEEE Transactions on Smart Grid, Vol. 8, Núm. 4, pp. 1932-1942

2016

  1. Effect of different design stages on the SEU failure rate of FPGA systems

    2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

  2. Intelligent gateway for industry 4.0-compliant production

    IECON Proceedings (Industrial Electronics Conference)

  3. SafeSoC: A fault-tolerant-by-redundancy evaluation card for high speed serial communications

    2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings

  4. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    Reliability Engineering and System Safety, Vol. 151, pp. 1-9