Publicaciones en las que colabora con Jagoba Arias Pérez (12)

2007

  1. Decompression dual core for SoPC applications in high speed FPGA

    IECON Proceedings (Industrial Electronics Conference)

  2. Hardware architecture for a general regression neural network coprocessor

    Neurocomputing, Vol. 71, Núm. 1-3, pp. 78-87

  3. OSCRYB: Open source CRYpto-bridge for secure ethernet point-to-point industrial communications

    IECON Proceedings (Industrial Electronics Conference)

2006

  1. Architecture of a real-time wavelet transform calculation SoPC core for industrial applications

    IECON Proceedings (Industrial Electronics Conference)

  2. Comparison of two designs for the multifunction vehicle bus

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

  3. Run-time reconfigurable hardware-software architecture for PID motor control IP cores

    IECON Proceedings (Industrial Electronics Conference)

  4. Simulink/modelsim simulable VHDL PID core for industrial SoPC multiaxis controllers

    IECON Proceedings (Industrial Electronics Conference)

2005

  1. A tiny microprocessor floating point implementation of a general regression neural network

    WSEAS Transactions on Computers, Vol. 4, Núm. 2, pp. 280-285

  2. Multiprocessor SoPC-core for FAT volume computation

    Microprocessors and Microsystems, Vol. 29, Núm. 10, pp. 421-434

2004

  1. Co-simulation virtual platform for reconfigurable multiprocessor hybrid cores development

    Proceedings of the International Conference on Modeling, Simulation and Visualization Methods, MSV'04 and Proceedings of the Int. Conference on Algorithmic Mathematics and Comput. Sci., AMCS'04

  2. High throughput serpent encryption implementation

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Run-time reconfigurable hybrid multiprocessor cores

    Proceedings of the IEEE International Conference on Industrial Technology