Voltage-source-inverters with legs connected in parallel

  1. Capellá Frau, Gabriel José
Dirigida por:
  1. Jordi Zaragoza Bertomeu Director/a
  2. Josep Pou Félix Director/a

Universidad de defensa: Universitat Politècnica de Catalunya (UPC)

Fecha de defensa: 26 de marzo de 2015

Tribunal:
  1. José Luis Martín Presidente
  2. Antoni Arias Pujol Secretario/a
  3. Jon Andreu Larrañaga Vocal

Tipo: Tesis

Teseo: 398470 DIALNET lock_openTDX editor

Resumen

The number of applications that require the use of power converters has been continually increasing in the last years on account of environmental and economical concerns. The power to be processed by these converters has been growing too. These applications include uninterruptible power supplies, motor drives, and distributed generation, such as solar photo-voltaic panels and wind turbines. The rated power of such converters can be raised by increasing the output currents. This can be chieved by connecting converter, converter legs or power devices in parallel. The connection of legs in parallel in a voltage ource inverter is made by means of inductors, hich can be either magnetically coupled or uncoupled. One of the issues that needs to be addressed is achieving an even contribution to the output current from all the legs. Current imbalances are due to circulating currents among the legs which must be avoided or controlled since they produce additional losses and stress to the power devices of the converter. An efficient technique to attain such a balance is presented in this thesis. The balancing technique achieves the objective regardless of the type of inductors used. In spite of the afore mentioned issues, the potential benefits of paralleling converter legs make their use a worthwhile option. Some of the additional benefits of paralleling are the improvement in the total harmonic distortion of the output current and voltage and the reduction of the output filters. Besides, inverters with legs connected in parallel are modular and because of that, their production and maintenance become less expensive. Moreover, they qualify for the implementation of fault-tolerant techniques thus offering the possibility to achieve systems with improved overall reliability. Interleaving of the carriers can be used to modulate the reference signals for each leg, which leads to a reduction in the output current ripple without resorting to increasing the switching frequency. A whole set of shifted carriers is required if interleaved pulse-width modulators are used. Implementing this by means of a digital signal processor (DSP) means that the higher the number of carriers, the higher the number of DSP timing resources required. Provided that the latter are usually limited, this could be a drawback when increasing the number of interleaved carriers. In this thesis the implementation of a pulse-width modulation (PWM) scheme where all modulators use the same carrier offering the same results as if a set of n interleaved carriers were used is presented. Since the proposed algorithm takes maximum benefit from the PWM units available in a DSP, a higher number of legs connected in parallel can be controlled without adding any external processing hardware. In multiphase voltage source inverters with n interleaved parallel-connected legs, the best single-phase output voltage is achieved when the carriers are evenly phase shifted. However, switching among nonadjacent levels can be observed at regular intervals in the line-to-line voltages, causing bad harmonic performance. This thesis includes a novel implementation of PWM that improves the quality of the line-to-line output voltages in interleaved multiphase voltage-source inverters. With the proposed method, switching in the line-to-line voltages happens exclusively between adjacent levels. The modulator utilizes two sets of n evenly phase-shifted carriers that are dynamically allocated. Because of its generality, the proposed implementation is valid for any number of phases and any number of legs in parallel. All the modulation and control algorithms proposed in this thesis have been firstly simulated on Matlab/Simulink models, and then experimentally corroborated on a low power laboratory prototype.