Estimating the resilience against single event upsets in applications implemented on sram based fpgas

Abstract

This thesis addresses the utilization of Custom Off The Shelf SRAM based FPGAs in environments with an elevated particle flux. The main focus lies on the development and application of suitable test methods for obtaining the exact SEU resilience of a given design.As a first step an external and non-invasive fault injection method is developed addressing the sparsity of fault injectors with low hardware overhead in the currently available state of the art. In a second step a performance improved fault injection method is developed, which includes a universal approach for handling issues related to fault injection using internal configuration ports.The proposed high performance fault injection platform is both mathematically characterized and evaluated in practice with special focus on different parameters that have a direct influence on the speed of the fault injection and also the accuracy of the obtained results.Finally, the proposed fault injection methods are used to investigate attributes important for fault tolerant applications. Detailed evaluations of the aspects of TMR granularity, SEU resiliences of common application circuits and the impact of adequate validation on the fault injection results are presented.